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參數(shù)資料
| 型號： | 62LV256SC |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 元件分類： | SRAM |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的128K的× 8位 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 40K |
| 代理商： | 62LV256SC |
IS62LV256
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. K
12/11/02
7
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2,3)
(Over Operating Range)
-45 ns
Min.
-70 ns
Min.
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
Parameter
Max.
Max.
Unit
Write Cycle Time
45
—
70
—
ns
CE
to Write End
35
—
60
—
ns
Address Setup Time to Write End
25
—
60
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
25
—
55
—
ns
Data Setup to Write End
20
—
30
—
ns
Data Hold from Write End
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with
OE
HIGH.
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