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參數資料
| 型號： | 7106L-R40-T |
| 廠商： | UNISONIC TECHNOLOGIES CO LTD |
| 元件分類： | ADC |
| 英文描述： | 1-CH PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO40 |
| 封裝： | LEAD FREE, SSOP-40 |
| 文件頁數： | 16/18頁 |
| 文件大小： | 438K |
| 代理商： | 7106L-R40-T |
7106
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
7 of 18
www.unisonic.com.tw
QW-R502-018.D
TYPICAL INTEGRATOR AMPLIFIER OUTPUT WAVEFORM (INT PIN)
DE-INTEGRATE PHASE
0 - 1999 COUNTS
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
AUTO ZERO PHASE
(COUNTS)
2999-1000
TOTAL CONVERSION TIME=4000 × tCLOCK=16,000 × tosc
DETAILED DESCRIPTION
ANALOG SECTION
Figure 1 shows the Analog Section for the UTC 7106. Each measurement cycle is divided into three phases. They
are(1) auto-zero(A-Z), (2)signal integrate (INT)and (3)de-integrate(DE).
AUTO-ZERO PHASE
During auto-zero three things happen. First, input high and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited
only by the noise of the system. In any case, the offset referred to the input is less than 10μV.
SIGNAL INTEGRATE PHASE
During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and
low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN
LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. if,
on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the
integrated signal is determined.
DE-INTEGRATE PHASE
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and
input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required
for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:
DISPLAY COUNT=1000( VIN/ VREF ).
DIFFERENTIAL INPUT
The input can accept differential voltages anywhere within the common mode range of the input amplifier, or
specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a
CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst
case condition would be a large positive common mode voltage with a near full scale negative differential input
voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V
of either supply without loss of linearity.
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| 7106G-D40-T | 1-CH PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDIP40 |
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| 7106L-QM1-Y | 1-CH PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
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