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參數資料
| 型號： | 71M6511-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 封裝： | LEAD FREE, LQFP-64 |
| 文件頁數： | 26/98頁 |
| 文件大?。?/td> | 1278K |
| 代理商： | 71M6511-IGTR/F |
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71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 32 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
Timer/Counter Control Register (TCON)
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 40: The TCON Register
Bit
Symbol
Function
TCON.7
TF1
Timer 1 overflow flag
TCON.6
TR1
Not used for interrupt control
TCON.5
TF0
Timer 0 overflow flag
TCON.4
TR0
Not used for interrupt control
TCON.3
IE1
External interrupt 1 flag
TCON.2
IT1
External interrupt 1 type control bit
TCON.1
IE0
External interrupt 0 flag
TCON.0
IT0
External interrupt 0 type control bit
Table 41: The TCON Bit Functions
Interrupt Request register (IRCON)
MSB
LSB
EX6
IEX5
IEX4
IEX3
IEX2
Table 42: The IRCON Register
Bit
Symbol
Function
IRCON.7
-
IRCON.6
-
IRCON.5
IEX6
External interrupt 6 edge flag
IRCON.4
IEX5
External interrupt 5 edge flag
IRCON.3
IEX4
External interrupt 4 edge flag
IRCON.2
IEX3
External interrupt 3 edge flag
IRCON.1
IEX2
External interrupt 2 edge flag
IRCON.0
-
Table 43: The IRCON Bit Functions
Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine
is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called).
External Interrupts
The external interrupts are connected as shown in Table 44. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to
achieve the edge polarity shown in Table 44.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
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| 71M6511-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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| 71M6511-IGTR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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| 71M6511H-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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