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參數資料
| 型號： | 71M6511-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 封裝： | LEAD FREE, LQFP-64 |
| 文件頁數： | 32/98頁 |
| 文件大?。?/td> | 1278K |
| 代理商： | 71M6511-IGTR/F |
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71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 38 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
DIO_DIR bit
0
1
DIO Pin Function
input
output
Table 53: DIO_DIR Control Bit
Values read from and written into the DIO ports use the data registers P0, P1 and P2.
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 52 for DIO pins
available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for
pulse counting. The control resources selectable for the DIO pins are listed in Table 54. If more than one input is connected to
the same resource, the resources are combined using a logical OR.
DIO_R
Value
Resource Selected for DIO Pin
0
NONE
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0 rising)
5
Low priority I/O interrupt (INT1 rising)
6
High priority I/O interrupt (INT0 falling)
7
Low priority I/O interrupt (INT1 falling)
Table 54: Selectable Controls using the DIO_DIR Bits
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,
VARPULSE = DIO7) using the I/O RAM registers DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and DIO7
are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I/O RAM register
DIO_EEX (0x2008[4]).
Physical Memory
Data bus address space is allocated to on-chip memory as shown in Table 55.
Address
(hex)
Memory
Technology
Memory Type
Typical Usage
Wait States
(at 5MHz)
Memory Size
(bytes)
0000-FFFF
Flash Memory
Non-volatile
Program and non-volatile
data
0
64KB
0000-07FF
Static RAM
Battery-buffered
MPU data
0
2KB
1000-13FF
Static RAM
Volatile
CE data
5
1KB
2000-20FF
Static RAM
Volatile
Configuration RAM
(I/O RAM)
0
256
3000-3FFF
Static RAM
Volatile
CE Program code
5
4KB
Table 55: MPU Data Memory Map
Flash Memory: The 71M6511 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
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