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參數資料
型號: 71M6521FE-IMR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC68
封裝: LEAD FREE, LQFN-68
文件頁數: 21/103頁
文件大小: 1691K
代理商: 71M6521FE-IMR/F
71M6521DE/71M6521FE
Energy Meter IC
DATA SHEET
OCTOBER 2010
Page: 24 of 103
2005-2010 Teridian Semiconductor Corporation
v1.1
A Maxim Integrated Products Brand
19-5370; 10/10
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor at up to 38,400
bits/s (with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6521DE/FE has several UART-related registers for the control and buffering of serial data. All UART transfers are
programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates
from 300 to 38400 bps. Table 13 shows how the baud rates are calculated. Table 14 shows the selectable UART operation
modes.
Using Timer 1
Using Internal Baud Rate Generator
UART 0
2
smod * f
CKMPU/ (384 * (256-TH1))
2
smod * f
CKMPU/(64 * (2
10-S0REL))
UART 1
N/A
fCKMPU/(32 * (2
10-S1REL))
Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the
SFR PCON. TH1 is the high byte of timer 1.
Table 13: Baud Rate Generation
UART 0
UART 1
Mode 0
N/A
Start bit, 8 data bits, parity, stop bit, variable baud
rate (internal baud rate generator)
Mode 1
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator or timer 1)
Start bit, 8 data bits, stop bit, variable baud rate
(internal baud rate generator)
Mode 2
Start bit, 8 data bits, parity, stop bit, fixed
baud rate 1/32 or 1/64 of fCKMPU
N/A
Mode 3
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator or
timer 1)
N/A
Table 14: UART Modes
Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as
those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial
modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated
by setting and reading the 9
th bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON.3) in the S0COn and S1CON
SFRs for transmit and RB81 (S1CON.2) for receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) can be used as
handshake signals for inter-processor communication in multi-processor systems.
Serial Interface 0 Control Register (S0CON).
The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.
MSB
LSB
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
Table 15: The S0CON Register
Serial Interface 1 Control Register (S1CON).
The function of the serial port depends on the setting of the Serial Port Control Register S1CON.
相關PDF資料
PDF描述
71M6521DE-IGT/F SPECIALTY ANALOG CIRCUIT, QFP64
71M6521FE-IGTR/F SPECIALTY ANALOG CIRCUIT, QFP64
71M6521DE-IMR/F SPECIALTY ANALOG CIRCUIT, QCC68
71M6521FE-IM/F SPECIALTY ANALOG CIRCUIT, QCC68
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