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| 型號： | 71M6531F-IM/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數(shù)： | 115/120頁 |
| 文件大小： | 2477K |
| 代理商： | 71M6531F-IM/F |
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
94
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
The maximum time jitter is 67 s and is independent of the number of pulses measured. Thus, if the pulse
generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm.
The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum
rate, it will simply output at its maximum rate without exhibiting any rollover characteristics. The actual
pulse rate, using WSUM as an example, is:
Hz
X
F
WSUM
WRATE
RATE
S
46
2
=
,
where FS = sampling frequency (2520.6 Hz) and X = Pulse speed factor (as defined in the CECONFIG
register with the PULSE_FAST and PULSE_SLOW bits).
Table 64: CE Pulse Generation Parameters
CE
Address
Name
Default
Description
0x21
WRATE
827
Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse. The
default value results in a Kh of 1.0 Wh/pulse when 2520 samples
are taken in each accumulation interval (and VMAX=600,
IMAX = 442 [for 400
Ω shunt], In_8 = 1, X = 6).
Maximum value = 2
15 -1.
0x41
APULSEW
0
Watt pulse generator input (see DIO_PW bit). The output pulse
rate is: APULSEW * FS * 2
-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
0x42
APULSER
0
VAR pulse generator input (see DIO_PV bit). The output pulse rate
is: APULSER * FS*2
-32 * WRATE * X * 2-14. This input is buffered and
can be loaded during a computation interval. The change will take
effect at the beginning of the next interval.
0x43
APULSE2
0
Third pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE2 * FS*2
-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
0x44
APULSE3
0
Fourth pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE3 * FS*2
-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
0x38
PULSE
WIDTH
12
Register for pulse width control of XPULSE and YPULSE. The max-
imum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default value
will generate pulses of 10 ms width at FS = 2520.62 Hz.
4.3.9
CE Calibration Parameters
Table 65 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 65: CE Calibration Parameters
CE
Address
Name
Default
Description
0x10
CAL_IA
16384
These constants control the gain of their respective channels. The
nominal value for each parameter is 2
14 = 16384. The gain of each
channel is directly proportional to its gain constant. Thus, if the
gain of the IA channel is 1% slow, CAL_IA should be scaled by
1/(1 – 0.01) and the resulting value is 16549.
0x11
CAL_VA
16384
0x12
CAL_IB
16384
0x13
CAL_VB
16384
0x18
PHADJ_A
0
These two constants control the CT phase compensation. No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. Range:
± 215 – 1. If it is
desired to delay the current by the angle
Φ, the equations are:
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