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參數資料
| 型號： | 71M6531F-IM/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數： | 60/120頁 |
| 文件大小： | 2477K |
| 代理商： | 71M6531F-IM/F |
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
44
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F)
DIO
40
41
42
43
44
45
–
47
48
49
50
51
LCD Segment
60
61
62
63
64
65
–
67
68
69
70
71
Pin number
95
97
98
40
31
38
–
22
23
24
25
50
Configuration (DIO
or LCD segment)
4
5
6
7
0
1
–
3
4
5
6
7
LCD_BITMAP[63:56]
LCD_BITMAP[71:64]
Data Register
L
C
D_S
E
G60[
0]
L
C
D_S
E
G61[
0]
L
C
D_S
E
G62[
0]
L
C
D_S
E
G63[
0]
L
C
D_S
E
G64[
0]
L
C
D_S
E
G65[
0]
–
L
C
D_S
E
G67[
0]
L
C
D_S
E
G68[
0]
L
C
D_S
E
G69[
0]
L
C
D_S
E
G70[
0]
L
C
D_S
E
G71[
0]
Direction Register
0 = input,
1 = output
L
C
D_S
E
G60[
0]
L
C
D_S
E
G61[
0]
L
C
D_S
E
G62[
0]
L
C
D_S
E
G63[
0
]
L
C
D_S
E
G64[
3]
L
C
D_S
E
G65[
3]
–
L
C
D_S
E
G67[
3]
L
C
D_S
E
G68[
3]
L
C
D_S
E
G69[
3]
L
C
D_S
E
G70[
3]
L
C
D_S
E
G71[
3]
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] bits and
data access is controlled with the LCD_SEGn[0] bits in I/O RAM.
DIO56 through DIO58 are dedicated DIO pins. They are controlled with DIO_DIR56[7] through
DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM.
1.5.9
Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2.
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
Since the control for DIO24 through DIO51 is shared with the control for LCD segments, the firmware
must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually,
this requires reading the I/O RAM register, applying a mask and writing back the modified byte.
Table 45: DIO_DIR Control Bit
DIO_DIR [n]
0
1
DIO Pin n Function
Input
Output
Table 46: Selectable Control using DIO_DIR Bits
DIO_R
Value
Resource Selected for DIO Pin
0
None
1
Reserved
2
T0 (counter 0 clock)
3
T1 (counter 1 clock)
4
High priority I/O interrupt (INT0 rising)
5
Low priority I/O interrupt (INT1 rising)
6
High priority I/O interrupt (INT0 falling)
7
Low priority I/O interrupt (INT1 falling)
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