- 您現在的位置：買賣IC網 > PDF目錄68811 > 71M6541D-IGT/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP64 PDF資料下載
參數資料
| 型號： | 71M6541D-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | LEAD FREE, LQFP-64 |
| 文件頁數： | 86/165頁 |
| 文件大小： | 2208K |
| 代理商： | 71M6541D-IGT/F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁當前第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁
v1.1
2008–2011 Teridian Semiconductor Corporation
27
2.3.6
Pulse Generators
The 71M6541D/F and 71M6542F provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE,
as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can
be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be configured to
generate interrupts to the MPU.
The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x210C[0]). When this bit is
set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.
The function of each pulse generator is determined by the CE code and the MPU code must configure the
corresponding pulse outputs in agreement with the CE code. For example, standard CE code produces a
mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE.
A common use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software
in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging.
A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about
to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the
V3P3SYS supply voltage actually drops.
2.3.6.1 XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins
SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE
outputs can be updated once on each pass of the CE code.
See 5.3 CE Interface Description on page 125 for details.
2.3.6.2 VPULSE and WPULSE
Referring to Figure 12, during each CE code pass the hardware stores exported WPULSE and VPULSE sign
bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them
over the multiplexer frame. As seen in Figure 12, the FIFO is reset at the beginning of each multiplexer
frame. As also seen in Figure 12, the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0])
controls the delay to the first pulse update and the interval between subsequent updates. The LSB of
the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if
PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in
Table 76.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX frame duration in units of CK_FIR clock cycles is given by:
If PLL_FAST=1:
MUX frame duration in CK_FIR cycles = [1 + (
FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]
If PLL_FAST=0:
MUX frame duration in CK_FIR cycles = [3 + 3*(
FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)]
PLS_INTERVAL[7:0] in units of CK_FIR clock cycles is calculated by:
PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 )
Since the FIFO resets at the beginning of each multiplexer frame, the user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE execution are output
before the multiplexer frame completes. For instance, the 71M654x CE code outputs six updates per
multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for
the interval is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth output occurs too late and
would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result).
Since one LSB of
PLS_INTERVAL[7:0] is equal to 4 CK_FIR clock cycles, the pulse time interval TI in units of
CK_FIR clock cycles is:
TI = 4*PLS_INTERVAL[7:0]
相關PDF資料 |
PDF描述 |
|---|---|
| 71M6542G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6541G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 71M6541F-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 71M6543F-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543H-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 71M6541D-IGTR/F | 功能描述:計量片上系統 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時鐘頻率:70 Hz 程序存儲器大小:64 KB 數據 RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數量:12 片上 ADC: 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6541DT-IGT/F | 制造商:Maxim Integrated Products 功能描述:ENERGY METER ICS - Rail/Tube |
| 71M6541DT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE SOC, 32KB FLASH, PRES TEMP SENSOR - Tape and Reel |
| 71M6541F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:71M6541D/71M6541F/71M6541G/71M6542F/71M6542G 是 TeridianTM 的第4 代高集成度單相電表SoC |
| 71M6541F-DB | 功能描述:開發板和工具包 - 8051 71M6541 Eval Kit RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
發布緊急采購，3分鐘左右您將得到回復。