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參數資料
| 型號： | 71M6541D-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | LEAD FREE, LQFP-64 |
| 文件頁數： | 102/165頁 |
| 文件大小： | 2208K |
| 代理商： | 71M6541D-IGTR/F |
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v1.1
2008–2011 Teridian Semiconductor Corporation
41
the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the
IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A).
Figure 16 shows the device interrupt structure.
Referring to Figure 16, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M654x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 16, and in Table 26 and
Table 27 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 38. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from interrupt instruction, RETI. When a RETI instruction is performed, the
processor returns to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, and then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the
interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the
following conditions are met:
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28).
The Timer/Counter control registers, TCON and T2CON (see
The interrupt request register, IRCON (see Table 31).
The interrupt priority registers: IP0 and IP1 (see Table 36).
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol
Function
IEN0[7]
EAL
EAL = 0 disables all interrupts.
IEN0[6]
WDT
Not used for interrupt control.
IEN0[5]
–
Not Used.
IEN0[4]
ES0
ES0 = 0 disables serial channel 0 interrupt.
IEN0[3]
ET1
ET1 = 0 disables timer 1 overflow interrupt.
IEN0[2]
EX1
EX1 = 0 disables external interrupt 1: DIO status change
IEN0[1]
ET0
ET0 = 0 disables timer 0 overflow interrupt.
IEN0[0]
EX0
EX0 = 0 disables external interrupt 0: DIO status change
Table 27: The IEN1 Bit Functions (SFR 0xB8)
Bit
Symbol
Function
IEN1[7]
–
Not used.
IEN1[6]
–
Not used.
IEN1[5]
EX6
EX6 = 0 disables external interrupt 6:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
IEN1[4]
EX5
EX5 = 0 disables external interrupt 5: EEPROM or SPI
IEN1[3]
EX4
EX4 = 0 disables external interrupt 4: VSTAT
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