- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68812 > 71M6543H-IGT/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | 71M6543H-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數(shù)： | 100/157頁 |
| 文件大小： | 2178K |
| 代理商： | 71M6543H-IGT/F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁當前第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
47
2.5
On-Chip Resources
2.5.1
Physical Memory
2.5.1.1 Flash Memory
The device includes 64 KB (71M6543F/H) or 128 KB (71M6543G/GH) of on-chip flash memory. The
flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and
I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective
locations.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) field
on the 71M6543F/H and the CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH define
which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at
1024*CE_LCTN[6/5:0] on the 71M6543F/H and at 1024*CE_LCTN[6:0] on the 71M6543G/GH.
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).
Table 39: Flash Memory Access
Access by
Access
Type
Condition
MPU
R/W/E
W/E only if CE is disabled.
CE
R
SPI
R/W/E
Access only when SFM is invoked (MPU halted).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) key is correctly programmed, the MPU may write to the
flash memory. This is one of the non-volatile storage options available to the user in addition to external
EEPROM.
The flash program write enable bit, FLSH_PSTWR (SFR 0xB2[0]), differentiates 80515 data store instructions
(MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware after
each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
If the CE is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has no effect when
CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time interval between
the CE code passes. During this delay time, the FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU
continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND bit
falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be first copied to RAM, followed by a page erase. After
this, the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
Write the pattern 0xAA to the FLSH_ERASE (SFR 0x94) register.
The mass erase cycle can only be initiated when the ICE port is enabled.
相關PDF資料 |
PDF描述 |
|---|---|
| 71M6543G-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543GH-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543GH-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 722BG | 2-OUTPUT DC-DC REG PWR SUPPLY MODULE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 71M6543H-IGTR/F | 功能描述:IC ENERGY METER 100-LQFP 制造商:maxim integrated 系列:Single Converter Technology? 包裝:帶卷（TR） 零件狀態(tài):停產(chǎn) 輸入阻抗:- 測量誤差:0.1% 電壓 - I/O 高:2V 電壓 - I/O 低:0.8V 電流 - 電源:- 電壓 - 電源:3 V ~ 3.6 V 表計類型:3 相 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應商器件封裝:100-LQFP（14x14） 標準包裝:1,000 |
| 71M6543HT-IGT/F | 制造商:Maxim Integrated Products 功能描述:ENERGY METER ICS - Rail/Tube |
| 71M6543HT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE SOC, 64KB FLASH, PRES TEMP SENSOR, HIGH PRES REF - Tape and Reel |
| 71M6545 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size |
| 71M6545H | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size |
發(fā)布緊急采購，3分鐘左右您將得到回復。