- 您現在的位置：買賣IC網 > PDF目錄68812 > 71M6543H-IGT/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP100 PDF資料下載
參數資料
| 型號： | 71M6543H-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數： | 113/157頁 |
| 文件大小： | 2178K |
| 代理商： | 71M6543H-IGT/F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁當前第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
59
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
PORT_E.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 48.
Example: SEGDIO12 (pin 32 in Table 48) is configured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured
as an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5
of LCD_SEG12.
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in Figure 12.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 48 lists the
internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If
more than one input is connected to the same resource, the resources are combined using a logical OR.
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Resource Selected for SEGDIOn or PB Pin
0
None
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0)
5
Low priority I/O interrupt (INT1)
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See Table 49.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in Figure 16, right), not source it from V3P3D (as shown in Figure 16, left). This is due
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 139.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pullup or pulldown resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
相關PDF資料 |
PDF描述 |
|---|---|
| 71M6543G-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543GH-IGTR/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543GH-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 722BG | 2-OUTPUT DC-DC REG PWR SUPPLY MODULE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 71M6543H-IGTR/F | 功能描述:IC ENERGY METER 100-LQFP 制造商:maxim integrated 系列:Single Converter Technology? 包裝:帶卷（TR） 零件狀態:停產 輸入阻抗:- 測量誤差:0.1% 電壓 - I/O 高:2V 電壓 - I/O 低:0.8V 電流 - 電源:- 電壓 - 電源:3 V ~ 3.6 V 表計類型:3 相 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應商器件封裝:100-LQFP（14x14） 標準包裝:1,000 |
| 71M6543HT-IGT/F | 制造商:Maxim Integrated Products 功能描述:ENERGY METER ICS - Rail/Tube |
| 71M6543HT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE SOC, 64KB FLASH, PRES TEMP SENSOR, HIGH PRES REF - Tape and Reel |
| 71M6545 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size |
| 71M6545H | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size |
發布緊急采購，3分鐘左右您將得到回復。