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參數資料
| 型號： | 73M1903C-IM/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | LEAD FREE, QFN-32 |
| 文件頁數： | 2/48頁 |
| 文件大小： | 487K |
| 代理商： | 73M1903C-IM/F |
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73M1903C Data Sheet
DS_1903C_033
10
Rev. 5.0
2.2
Slave Mode and DAISY CHAIN
If the SCLK pin is externally pulled down to ground by a <4.7K
resistor, the 79M1903C device is in the
slave mode, after reset. In this mode of operation the serial clock (SCLK) and
FS are inputs to
79M1903C provided by the Master device. The serial clock input must be connected to OSCIN pin while
SCLK pin of 73M1903C is unconnected, except for the resistor connected to ground (see Figures 4 and
5). The 73M1903C PLL must be programmed to multiply the serial clock frequency by an appropriate
factor in order to obtain Fsys. Therefore the serial clock has to be continuous and without low frequency
jitter (the high frequency jitter is rejected by the 79M1903C PLL). The SckMode pin is not used since the
Master device provides
FS and serial clock.
Figure 4: 73M1903C Host Connection in Master and Slave Modes
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Master)
SckMode
"1/0"
FS
SCLK
SDIN
SDOUT
MCLK
HOST
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Slave)
FSBD
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Slave)
FS
SCLK
SDIN
SDOUT
HOST
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Slave)
FSBD
Daisy chain for Master/Slave mode
Daisy chain for Slave mode
(Slave)
(Master)
SckMode
TYPE
"x"
SckMode
TYPE
"x"
TYPE
"1/0"
SckMode
TYPE
"x"
"x" : don't care
Figure 5: 73M1903C Daisy Chaining for Master/Slave Mode and Slave Modes
In order to daisy chain two or more 73M1903C devices, the master must be programmed into hardware
controlled control frame mode by setting the HC bit (bit 0 in Register01) to 1, then set FSDEn (bit 3 in
Register06), and then set CkoutEn bit (bit 3 in Register01) to allow the
FSD to come through. The first
frame after enabling
FSD must be Data. For the two daisy chained devices, the data/control frames are
32 bits. The first 16 bits go to the first device; the next 16 bits go to the second device in the chain, as
timed by
FSD of the first device. For four daisy-chained devices, the data/control frames are 64 bits. The
first 16 bits go to the first device in the chain; the next 16 bits go to the second device in the chain as
started by
FSD of the first device, etc. FSD is always ”Late Type” frame sync.
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Master)
SckMode
"1/0"
FS
SCLK
SDIN
SDOUT
MCLK
HOST
SCLK
FS
OSCIN
SDIN
SDOUT
73M1903C
(Slave)
SckMode
FS
SCLK
SDIN
SDOUT
HOST
73M1903C Master Mode
73M1903C Slave Mode
(Master)
(Slave)
TYPE
"1/0"
TYPE
"x"
"x" : don't care
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