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參數資料
| 型號： | 73S8024C-ILR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | LEAD FREE, SOP-28 |
| 文件頁數： | 22/22頁 |
| 文件大小： | 471K |
| 代理商： | 73S8024C-ILR/F |
DS_8024C_023
73S8024C Data Sheet
Rev. 1.3
9
Figure 2: Power Down Mode Operation
8
Activation Sequence
The 73S8024C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of VDD > VDDF
The following steps and
or upon exit of Power-Down mode. The card interface may only be activated when
OFF is
high which indicates a card is present. No activation is allowed at this time.
CMDVCC (edge triggered)
must then be set low to activate the card.
Figure 3 show the activation sequence and the timing of the card control signals
when the system controller sets
CMDVCC low while the RSTIN is low:
1.
CMDVCC is set low.
2.
Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, then OFF goes
low to report a fault to the system controller, and the power VCC
3.
Turn I/O (AUX1, AUX2) to reception mode at the end of t
to the card is shut down.
2
4.
Due to the fall of RSTIN, CLK is applied to the card at the end of t
.
3
5.
RST is a copy of RSTIN after t
.
4. RSTIN may be set high before t 4, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
Figure 3: Activation Sequence – RSTIN low when
CMDVCC goes low
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 s, I/O goes to reception state
t3 = >0.5 s, CLK starts
t4
≥ 42000 card clock cycles (time for RST to become the copy of RSTIN)
CMDVCC
VCC
IO
CLK
RSTIN
t1
t2
t3
t4
RST
PRES
OFF
PWRDN
Internal RC OSC
CMDVCC
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
EMV / ISO deactivation
time ~= 100 uS
~10ms
PWRDN has effect when
the cardi s deactivated
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 73S8024RN | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Low Cost Smart Card Interface |
| 73S8024RN-20IM/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN-20IM/F1 | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN-20IMR/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN-20IMR/F1 | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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