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參數(shù)資料
| 型號： | 74125 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Quad 3-STATE Buffer |
| 中文描述： | 四三態(tài)緩沖器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 62K |
| 代理商： | 74125 |
2000 Fairchild Semiconductor Corporation
DS006387
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS125A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
A
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
Hi-Z
=
3-STATE (Outputs are disabled)
Order Number
DM74LS125AM
DM74LS125ASJ
DM74LS125AN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
Y
L
H
Hi-Z
A
L
H
X
C
L
L
H
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