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參數資料
| 型號： | 74LV4316D-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16 |
| 文件頁數： | 2/16頁 |
| 文件大小： | 156K |
| 代理商： | 74LV4316D-T |
Philips Semiconductors
Product specification
74LV4316
Quad bilateral switches
1998 Jun 23
10
WAVEFORMS
VM = 1.5 V at 2.7 V ≤ VCC ≤ 3.6 V
VM = 0.5 × VCC at 2.7 V > VCC > 3.6 V
VOL and VOH are the typical output voltage drop that occur with the
output load
Vx = VOL + 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V
VX = VOL + 0.1 × VCC at 2.7 V >VCC > 3.6 V
VY = VOH – 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V
VY = VOH – 0.1 × VCC at 2.7 V >VCC > 3.6 V
SV01638
V M
INPUTS
OUTPUTS
GND
V OL
V I
V OH
tPHL
tPLH
Figure 12. Input (Vis) to output (Vos) propagation delays.
SV01640
outputs
disabled
outputs
enabled
outputs
enabled
tPHZ
tPZH
tPZL
tPLZ
VX
VY
VM
INPUTS
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
OUTPUT
LOW-to-OFF
OFF-to-LOW
GND
VCC
VI
VOL
VOH
GND
Figure 13. Turn-on and turn-off times
for the inputs (nS, E) to the output (Vos).
TEST CIRCUIT
VM
tW
NEGATIVE
PULSE
10%
90%
0V
VM
tW
VI
POSITIVE
PULSE
90%
10%
0V
tTHL (tf)
tTLH (tr)tTHL (tf)
tTLH (tr)
VM = 1.5V
Input Pulse Definition
SY00044
SWITCH POSITION
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CL= 50pF
RL = 1k
Vcc
Test Circuit for Outputs
Open
GND
S1
VS1
DEFINITIONS
VCC
VI
< 2.7V
2.7–3.6V
VCC
2.7V
TEST
S1
tPLZ/tPZL
tPLH/tPHL
tPHZ/tPZH
VS1
Open
GND
VS1
≥ 4.5 V
2
< VCC
VCC
2
< VCC
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of
pulse generators.
VI
2
< VCC
RL = 1k
Figure 14. Load circuitry for switching times.
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相關代理商/技術參數 |
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