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參數資料
| 型號： | 74LVC161PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 1/22頁 |
| 文件大小： | 0K |
| 描述： | IC SYNC 4BIT BIN COUNTER 16TSSOP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 96 |
| 系列： | 74LVC |
| 邏輯類型： | 二進制計數器 |
| 方向： | 上 |
| 元件數： | 1 |
| 每個元件的位元數： | 4 |
| 復位： | 異步 |
| 計時： | 同步 |
| 計數速率： | 150MHz |
| 觸發器類型： | 正邊沿 |
| 電源電壓： | 1.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 74LVC161PW 74LVC161PW-ND 935210530112 |
1.
General description
The 74LVC161 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins
CP, PE, CET and CEP (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL
(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:
It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
2.
Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive edge-triggered clock
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous
reset
Rev. 6 — 30 September 2013
Product data sheet
f
max
1
t
PHL max
t
su
+
-----------------------------------
=
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LVC161PW118 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| 74LVC161PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LVC161PW-T | 功能描述:計數器 IC 3.3V SYNC 4-BIT BIN COUNTER RoHS:否 制造商:NXP Semiconductors 計數器類型:Binary Counters 邏輯系列:74LV 位數:10 計數法: 計數順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74LVC162244 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-State |
| 74LVC162244A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-State |
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