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參數(shù)資料
| 型號： | 78P7200L-IH |
| 廠商： | TDK Corporation |
| 英文描述： | E3/DS3/STS-1 Transceiver |
| 中文描述： | E3/DS3/STS-1收發(fā)器 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 171K |
| 代理商： | 78P7200L-IH |
78P7200
E3/DS3/STS-1
Line Interface Unit
TRANSMITTER
The transmitter accepts CMOS logic level clock
(TCLK), positive data (TPOS) and negative data
(TNEG) signals and generates high current drive
pulses on the LOUT+ and LOUT- pins. When
properly connected to a center tapped transformer,
an AMI pulse is generated which can drive a 75
coaxial cable.
Figure 3 shows the timing for the transmitter logic
signals. The output pulse width is internally set and
is not sensitive to input clock (TCLK) pulse width.
When a recommended transformer is used and
option pins are properly set, the transmitted pulse
shape at the end of a 75
terminated cable of 0 to
450 feet will fit the template for DSX3 pulse
published
in
ANSI
TR-NWT-000499 documents.
For 51.84 Mbit/s STS-1 application the transmitted
pulse for a short cable meets the requirements of
Bellcore
GR-253-CORE.
application, the transmitted pulse for a short cable
meets the requirements of ITU-T G.703 when both
LBO and
OPT!
pins are set LOW.
Page: 3 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
T1.102-1993,
Bellcore
For
34
Mbit/s
E3
The 78P7200 incorporates a selectable Line
Buildout (LBO) pulse shaper in the transmitter path.
For STS-1 and DS3 applications, the LBO pin
should be set HIGH if the cable is shorter than 225
feet and set LOW for longer cable lengths. For E3
application, LBO pin should be set LOW regardless
of cable length.
The
OPT!
pin is set HIGH for DS3 and STS-1
operation. The
OPT!
pin should be set LOW for E3
applications.
The
OPT@
pin should be set HIGH for normal
operation. By setting the
OPT@
pin to LOW it disables
the transmitter drivers and reduces the power
consumption of the circuit by approximately 125 mW.
Recommended settings for
OPT!
and LBO pins
SPEED
DS3/STS1
DS3/STS1
E3
CABLE
< 225'
> 225'
ALL
OPT!
HI
HI
LOW
LBO
HI
LOW
LOW
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