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參數資料
| 型號： | 78P7200L-IH |
| 廠商： | TDK Corporation |
| 英文描述： | E3/DS3/STS-1 Transceiver |
| 中文描述： | E3/DS3/STS-1收發器 |
| 文件頁數： | 8/11頁 |
| 文件大小： | 171K |
| 代理商： | 78P7200L-IH |
78P7200
E3/DS3/STS-1
Line Interface Unit
RECEIVER
(continued)
Page: 8 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
PARAMETER
Receive clock period
CONDITIONS
CL = 15 pF
MIN
NOM
22.35
19.29
29.1
12.24
9.65
14.55
4.5
MAX
6
UNIT
ns
ns
ns
ns
ns
ns
ns
DS3
STS-1
TRCF
E3
DS3
STS-1
Receive clock pulse width
TRC
E3
Receive clock positive
transition time
Receive clock negative
transition time
Positive or negative TRDP/ TRDN
receive data pulse width
TRCPT
TRCNT
CL = 15 pF
4.5
6
ns
60 - 300 kHz
10 - 800 kHz
10 - 800 kHz
VIN (min) = ±90 mV, short cable
10 Hz to 2.3 kHz STS-1, DS3
100 Hz to 10 kHz
All 1's data pattern,
KD = 0.418/RFO
DS3
STS-1
22.35
19.29
29.1
11.18
9.65
14.55
11.18
9.65
14.55
ns
ns
ns
ns
ns
ns
ns
ns
ns
UIPP
E3
DS3
STS-1
5
5
5
5
13.7
13.7
Receive data set-up timeTRDPS/ TRDNS
E3
DS3
STS-1
Receive data hold timeTRDPH/ TRDNH
E3
DS3
STS-1
0.3
E3
E3
0.15
0.20
UIPP
UIPP
Receive input jitter tolerance high
frequency (See Note)
10
10
72
12
UIPP
UIPP
μA/Rad
μA/Rad
μA/Rad
Mrad/
sec. -Volt
Receive input jitter tolerance
low frequency (See Note)
E3
DS3
STS-1
E3
80
92
62
14.5
88
17
Clock Recovery Phase
Detector Gain
KD
Clock Recovery Phase
Locked Oscillator Gain
KO
Note: UI (Unit Interval) defined as 22.35 ns for DS3, 29.1 ns for E3 and 19.29 ns for STS-1.
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