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參數資料
| 型號： | 88I8030 |
| 英文描述： | 88i8030 Serial ATA Bridge |
| 中文描述： | 88i8030串行ATA橋 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 117K |
| 代理商： | 88I8030 |
S
S
PRODUCT OVERVIEW
The 88i8030 family of Serial ATA (SATA) bridge chips, the Trst offering in the Marvell
input/output (I/O) solutions, allows storage OEMs to take advanced data storage systems to the next level of
performance. By converting Parallel ATA to SATA, the Marvell 88i8030 bridge solution allows Hard Disk Drive
(HDD), motherboard and storage subsystem manufacturers to utilize their current Parallel ATA electronics for
faster time-to-market prior to full industry transition to SATA. The 88i8030 devices are designed to interface to
traditional Parallel ATA HDD controllers as well as to host chipsets running up to 150 MBps. Since the bridge allows
parallel connectivity over short trace distances, the 88i8030 product allows for 150 MBps transfer rates with low
noise and high reliability. The devices employ the latest SATA Physical Layer (PHY) technology, starting with the
SATA Working Group-deTned Generation I speed of 1.5 Gbps, and scalable to 3.0 Gbps to support the future
Generation II, Phase II, SATA speed. The 88i8030s PHY leverages four generations of production-proven
Serializer/Deserializer (SERDES) technology from its industry-leading Alaska
bridge device implements user-selectable SSC for reduced EMI in storage systems. This makes the interface
attractive not only as an inside-the-box technology, but also potentially increases its usefulness for out-of-the-box
interconnects in many consumer electronics applications. The 88i8030 products offer premphasis and amplitude
settings with programmable coefTcients to help ensure signal integrity over extended trace and cable lengths.
This advanced signaling capability allows for optimal performance in many varieties of storage applications.
¨
family of high-speed interface
¨
Gigabit PHY products. The Marvell
FEATURES
BENEFITS
￥
Supports both host and device operation
￥
Enables faster system development
￥
User-selectable maximum speeds of 66/100/133/150 MBps
￥
Provides exibility in system design
￥
Ultra low power consumption
￥
Helps to extend battery life in mobile applications and lessen cooling
requirements in storage enclosures
￥
Supports spec-deTned power management
￥
EfTcient power consumption control
￥
Advanced design tolerates +/- 1.5% frequency offset
￥
Allows for the use of less expensive ceramic resonators, lowering
system cost
￥
User-selectable Spread Spectrum Clocking (SSC) support
￥
Reduces Electro Magnetic Interference (EMI), key for both storage
systems and PC motherboards
￥
Programmable reference clock settings
￥
Increase design exibility
￥
Fully-digital Phase Locked Loop (PLL)
￥
Reduces sensitivity to process variations, increasing
manufacturability
￥
Pre-emphasis and amplitude settings with programmable coefTcients
￥
Ensure signal integrity over extended backplane distances up to
20+ inches of FR4 trace
Fig 1. 88i8030 Block Diagram
PHY
Link, Transport and
Command Layers
Register
FIFO
Test/Debug
CNFG
UART
PLL
Serial ATA
Parallel ATA
Serial ATA
Bridge Chip Solutions
88i8030
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