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參數(shù)資料
| 型號： | 9176CM-03 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.300 INCH, MS-013, MO-119, SOIC-28 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 224K |
| 代理商： | 9176CM-03 |
3
ICS9176C-03
Timing Diagrams
Timing in Divide by1 Mode
Timing in Divide by 2 Mode
Note:
In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is
transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD.
Timing in Power-down Mode
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