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參數資料
| 型號： | 9176CM-03LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.300 INCH, MS-013, MO-119, SOIC-28 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 224K |
| 代理商： | 9176CM-03LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9176C-03
9176C-03 Rev D 01/29/02
3.3 or 5.0 volt supply operation
±500 skew (max) between input and outputs
±250ps skew (max) between outputs
10 symmetric, TLL-compatible outputs
28-pin SOIC package
High drive, 40mA outputs
Power-down option
Output frequency range 25 MHz to 120 MHz
Input frequency range 25 MHz to 100 MHz
Ideal for PCI bus applications
Selection Table
Low Skew Output Buffer
The IC9176C-03 is designed specifically
to support the
tight
timing
requirements
of
high-performance
microprocessors and chip sets.
Because the jitter of the
device is limited to ±250ps, the ICS9176C-03 is ideal for
clocking Pentium systems. the 10 high drive (40mA), low-
skew (±250ps) outputs make the ICS9176C-03 a perfect fit
for PCI clocking requirements.
The ICS9176C-03 has 10 outputs synchronized in phase and
frequency to an input clock. The internal phase locked loop
(PLL) acts either as 1X clock multiplier or a 1/2X clock
multiplier depending on the state of the input control pins T0
and T1. With metal mask options, any type of ratio between
the input clock and output clock can be achieved, including
2X.
The PLL maintains the phase frequency relationship between
the input clock and the outputs by externally feeding back
FBOUT to FBIN. Any change in the input will be tracked by
all 10 outputs.
However, the change at the outputs will
happen smoothly so no glitches will be present on any driven
input.
The PLL circuitry matches rising edges of the input
clock and the output clock. Since the input to FBIN skew is
guarenteed to ±500ps, the part acts as a "zero delay" buffer.
The ICS9176C-03 has a total of eleven ouputs. Of these,
FBOUT is dedicated as the feedback into the PLL and another,
Q/2, has an output frequency half that of the remaining nine.
These nine outputs can either by running at the same speed as
the input, or at half the frequency of the input. With Q/2 as
the feedback to FBIN, the nine 'Q' outputs will be running at
twice the input frequency in the normal divide-by-1 mode.
In this case, the output can go to 120 MHz with a 60 MHz
input clock. The maximum rise and fall time of an output is
14ns and each is TTL-compatible with a 40mA symmetric
drive.
The ICS9176C-03 is fabricated using CMOS technology
which results in much lower power consumption and cost
compared with the gallium arsenide based 1086E. The typical
operating current for the ICS9176C-03 is 60mA versus 115mA
for the GA1086E.
Block Diagram
1
T0
Tn
o
i
t
p
i
r
c
s
e
D
00
n
w
o
d
-
r
e
w
o
P
01
)
s
t
u
p
t
u
o
=
K
L
C
f
O
L
P
(
e
d
o
M
t
s
e
T
10
)
n
O
L
P
(
l
a
m
r
o
N
11
e
d
o
M
2
y
b
e
d
i
v
i
D
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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