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參數資料
| 型號： | 9176CM-03LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.300 INCH, MS-013, MO-119, SOIC-28 |
| 文件頁數： | 7/8頁 |
| 文件大小： | 224K |
| 代理商： | 9176CM-03LF |
7
ICS9176C-03
Applications
FBOUT is normally connected to FBIN to facilitate input to
output skew control. However, there is no requirement that
the external feedback connection be a direct hardwire from an
output pin to the FBIN pin. As long as the signal at FBIN is
drived directly from the FBOUTpin and maintains its frequency,
additional delays can be accommodated. The clock phase of
the outputs (rising edge) will be adjusted so that the phase of
FBIN and ithe input clock will be the same. See Figure 1 for an
example.
In Figure 1, the propagation delay through the divide by 2
circuit is eliminated. The internal phase-locked loop will adjust
the output clock on the ICS9176C-03 to ensure zero phase
delay between the FBIN and CLK signals, as a result, the
rising edge at the output of the divide by two circuit will be
aligned with the rising edge of the 66 MHz input clock. This
type of configuration can be used to eliminate propagation
delay as long as the signal at FBIN is continuous and is not
gated or conditional.
The ICS9176C-03 is also ideal for clocking multi-processor
systems. The 10 outputs can be used to synchonize the
operation of CPU cache and memory banks operating at
different speeds. Figure 2 depicts a 2-CPU system in which
processors and associated periperals are operating at 66 MHz.
Each of the nine outputs operating at 66 MHz are fully utilized
to drive the appropriate CPU, cache and memory control logic.
The 33 MHz output is used to synchronize the operation of
the slower memory bank to restart of the system.
Figure 1
Figure 2
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