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參數(shù)資料
| 型號： | 9179BF-03LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9179 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 273K |
| 代理商： | 9179BF-03LF-T |
7
ICS9179-03
0258K 12/15/08
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
RDSP
VO = VDD*(0.5)
10
24
Output Impedance
RDSN
VO = VDD*(0.5)
10
24
Output High Voltage
VOH
IOH = -30 mA
2.3
3
V
Output Low Voltage
VOL
IOL = 23 mA
0.27
0.4
V
Output High Current
IOH
VOH = 2.0 V
-115
-54
mA
Output Low Current
IOL
VOL = 0.8 V
40
57
mA
Rise Time
1
Tr
VOL = 0.4 V, VOH = 2.4 V
0.5
0.95
1.33
ns
Fall Time
1
Tf
VOH = 2.4 V, VOL = 0.4 V
0.5
0.95
1.33
ns
Duty Cycle
1
Dt
VT = 1.5 V
455055%
Skew
1
Tsk
VT = 1.5 V
110
250
ps
TPHL1
VT = 1.5 V
1
5.2
5.5
ns
TPLH1
VT = 1.5 V
1
5.2
5.5
ns
Propagation
1,2
TPHL2
50% Buffer In to 90% Out
1
4.3
5
ns
TPLH2
50% Buffer In to 10% Out
1
4.3
5
ns
TEN
VT = 1.5 V
1
8
ns
TDIS
VT = 1.5 V
18
ns
Note2: Duty cycle of input clock is 47.5% to 52.5%. Input edge rate is for propagation delay
≥ 1V/ns
Note1: Paramater is guaranteed by design and characterization for all operating frequencies, (10MHz - 133MHz).
Not 100% tested in production
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