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參數(shù)資料
| 型號： | 9179F-06 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 244K |
| 代理商： | 9179F-06 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9179-06
0261G—07/21/03
Block Diagram
Zero Delay Buffer for PC133 SDRAMs
Pin Configuration
The ICS9179-06 generates low skew SDRAM clocks
required by high-speed RISC or CISC based
microprocessor systems.The ICS9179-06 is a zero delay
buffer with low output-to-output skew. The buffer is
compatible with Spread Spectrum clocks such as those
provided by the ICS 9248-55.
Individual outputs can be disabled via the I2C interface for
reduced power consumption and EMI. The nominal delay
for the ICS9179-06 can also be programmed to either 0.0,
-2.6, +2.1 or -0.7 ns via the I2C interface. An output enable
pin eases testability.
16-out zero delay buffer
Supports up to 4 PC133 SDRAM DIMMs
Spread Spectrum compatible
I
2C Interface
Four nominal input-to-output delays from +2.1 to
–2.6 ns selectable via I
2C
250 ps output-to-output skew
33 MHz to 133 MHz operating frequency
Multiple VDD, VSS pins for noise reduction
1.5V/ns minimum slew rate into 30 pF load
VDD = 3.3V +/-5%, Commercial temperature range
All outputs except FB_OUT tri-state with OE low.
48-pin SSOP package
48-Pin SSOP
Functionality
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