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參數資料
| 型號： | 9179F-06 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 244K |
| 代理商： | 9179F-06 |
2
ICS9179-06
0261G—07/21/03
Pin Descriptions
Power Groups
VDD = Power supply for OUTPUT buffers
VDDS = Power supply for I
2C circuitry
VDDA = Power supply for Analog PLL circuitry
Notes:
1.
At power up all sixteen outputs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well
for complete platform flexibility.
4.
I
2C Byte0, bits 0 & 1 used to select delay. Default* values at power up are 0
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P
Ground Groups
GND = Ground supply for OUTPUT buffer
GNDS = Ground supply for I
2C circuitry
GNDA = Ground supply for Analog PLL circuitry
Delay Selection Table
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-
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