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參數資料
| 型號： | 933656140623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 50 MHz, PDSO16 |
| 封裝： | PLASTIC, SOT-109, SO-16 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 146K |
| 代理商： | 933656140623 |
Philips Semiconductors
Product specification
NE/SE564
Phase-locked loop
1
1994 Aug 31
853-0908 13720
DESCRIPTION
The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor.
FEATURES
Operation with single 5V supply
TTL-compatible inputs and outputs
Guaranteed operation to 50MHz
External loop gain control
Reduced carrier feedthrough
No elaborate filtering needed in FSK applications
Can be used as a modulator
Variable loop gain (externally controlled)
APPLICATIONS
High speed modems
FSK receivers and transmitters
Frequency Synthesizers
PIN CONFIGURATIONS
V+
LOOP FILTER
D, N Packages
TTL OUTPUT
LOOP GAIN CONTROL
INPUT TO PHASE COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
FROM VCO
LOOP FILTER
FM/RF INPUT
BIAS FILTER
GND
HYSTERESIS SET
ANALOG OUT
FREQ. SET CAP
VCO OUT 2
V+
VCO OUT TTL
FREQ. SET CAP
TOP VIEW
SR01025
Figure 1. Pin Configuration
Signal generators
Various satcom/TV systems
pin configuration
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Plastic Small Outline (SO) Package
0 to +70
°C
NE564D
SOT109-1
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70
°C
NE564N
SOT38-4
16-Pin Plastic Dual In-Line Package (DIP)
-55 to +125
°C
SE564N
SOT38-4
BLOCK DIAGRAM
LIMITER
VCO
PHASE
COMPARATOR
SCHMITT
TRIGGER
RETRIEVER
DC
AMPLIFIER
POST DETECTION
PROCESSOR
1
2
3
45
6
7
8
9
10
11
12
13
14
15
16
V+
SR01026
Figure 2. Block Diagram
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