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參數資料
| 型號： | 934055780127 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | 50 A, 150 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247 |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 95K |
| 代理商： | 934055780127 |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
PHW50NQ15T
FEATURES
SYMBOL
QUICK REFERENCE DATA
’Trench’ technology
Very low on-state resistance
V
DSS = 150 V
Fast switching
Low thermal resistance
I
D = 50 A
R
DS(ON) ≤ 35 m
GENERAL DESCRIPTION
PINNING
SOT429 (TO247)
N-channel
enhancement
mode
PIN
DESCRIPTION
field-effect power transistor in a
plastic envelope using ’trench’
1
gate
technology.
2
drain
Applications:-
d.c. to d.c. converters
3
source
switched mode power supplies
tab
drain
The PHW50NQ15T is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j = 25 C to 175C
-
150
V
DGR
Drain-gate voltage
T
j = 25 C to 175C; RGS = 20 k
-
150
V
GS
Gate-source voltage
-
± 20
V
I
D
Continuous drain current
T
mb = 25 C
-
50
A
T
mb = 100 C
-
36
A
I
DM
Pulsed drain current
T
mb = 25 C
-
200
A
P
D
Total power dissipation
T
mb = 25 C
-
250
W
T
j, Tstg
Operating junction and
- 55
175
C
storage temperature
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS = 47 A;
-
460
mJ
energy
t
p = 100 s; Tj prior to avalanche = 25C;
V
DD ≤ 50 V; RGS = 50 ; VGS = 10 V; refer
to fig;15
I
AS
Non-repetitive avalanche
-
50
A
current
d
g
s
2
3
1
August 1999
1
Rev 1.000
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