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參數資料
| 型號： | 934055782127 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | 35 A, 200 V, 0.07 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247 |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 93K |
| 代理商： | 934055782127 |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
PHW35NQ20T
FEATURES
SYMBOL
QUICK REFERENCE DATA
’Trench’ technology
Very low on-state resistance
V
DSS = 200 V
Fast switching
Low thermal resistance
I
D = 35 A
R
DS(ON) ≤ 70 m
GENERAL DESCRIPTION
PINNING
SOT429 (TO247)
N-channel
enhancement
mode
PIN
DESCRIPTION
field-effect power transistor in a
plastic envelope using ’trench’
1
gate
technology. The device has very
low
on-state
resistance.
It
is
2
drain
intended for use in dc to dc
converters and general purpose
3
source
switching applications.
tab
drain
The PHW35NQ20T is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j = 25 C to 175C
-
200
V
DGR
Drain-gate voltage
T
j = 25 C to 175C; RGS = 20 k
-
200
V
GS
Gate-source voltage
-
± 20
V
I
D
Continuous drain current
T
mb = 25 C
-
35
A
T
mb = 100 C
-
25
A
I
DM
Pulsed drain current
T
mb = 25 C
-
140
A
P
D
Total power dissipation
T
mb = 25 C
-
250
W
T
j, Tstg
Operating junction and
- 55
175
C
storage temperature
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS = 35 A;
-
462
mJ
energy
t
p = 100 s; Tj prior to avalanche = 25C;
V
DD ≤ 50 V; RGS = 50 ; VGS = 10 V; refer
to fig:15
I
AS
Non-repetitive avalanche
-
35
A
current
d
g
s
2
3
1
August 1999
1
Rev 1.000
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