
1996 Jan 26
15
Philips Semiconductors
Objective specication
I2C-bus controlled PAL/NTSC TV processors
TDA8376; TDA8376A
Table 12 Vertical divider mode
Table 13 Video identication mode
Table 14 Long blanking mode
Table 15 EHT tracking mode
Table 16 Enable vertical guard (RGB blanking)
Table 17 Service blanking
Table 18 Overvoltage input mode
Table 19 Vertical deection mode (TDA8376 only)
NCIN
VERTICAL DIVIDER MODE
0
normal operation
1
switched to search window
VID
VIDEO IDENTIFICATION MODE
0
1 loop switched on and off
1
not active
LBM
BLANKING MODE
0
adapted to standard (50 or 60 Hz)
1
xed in accordance with 50 Hz standard
HCO
TRACKING MODE
0
EHT tracking only on vertical
1
EHT tracking on vertical and E-W
EVG
VERTICAL GUARD MODE
0
not active
1
active
SBL
SERVICE BLANKING MODE
0off
1on
PRD
OVERVOLTAGE MODE
0
detection mode
1
protection mode
EXP
CL
VERTICAL DEFLECTION MODE
0
normal
0
1
compress
1
0
expand
1
expand and lift
Table 20 Condition Y/C input
Table 21 PAL/NTSC matrix
Table 22 Y-delay adjustment; note 1
Note
1. For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
Table 23 RGB blanking
Table 24 Noise coring (peaking)
Table 25 Enable fast blanking RGB1
Table 26 Enable fast blanking RGB2
CVS
Y-INPUT MODE
0
switched to Y/C mode
1
switched to CVBS mode
MAT
MATRIX
0
adapted to standard
1PAL
YD0 to YD3
Y-DELAY
YD3
× 160 ns +
YD2
× 80 ns +
YD1
× 40 ns +
YD0
× 40 ns
RBL
RGB BLANKING
0
not active
1
active
COR
NOISE CORING
0off
1on
IE1
FAST BLANKING
0
not active
1
active
IE2
FAST BLANKING
0
not active
1
active