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參數資料
| 型號： | 935187130557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數： | 43/43頁 |
| 文件大小： | 250K |
| 代理商： | 935187130557 |
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February 1995
9
Philips Semiconductors
Preliminary specication
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
FUNCTIONAL DESCRIPTION
Acquisition area
The acquisition area is in the centre of the visible screen
area. Vertically 228 lines are sampled. Horizontally
672 Y-pixels are processed. The exact active processing
area can be fine tuned in horizontal (2 pixels/steps,
16 steps) and vertical (1 line/step, 16 steps) direction for
both main and sub-channel by the I2C-bus (see Fig.3). The
given numbers are pixel numbers at a 13.5 MHz data rate.
The signals, which are dependent on the I2C-bus registers,
can also be related to the Hsync, in which event they are
delayed by 68 pixels.
Chrominance format
The chrominance format is 4 : 1 : 1.
The YUV signals are sampled at a rate of 27 MHz and then
filtered and subsampled to a data rate of 13.5 MHz.
It is expected that the input signals do not contain
frequencies outside the video bandwidth (YBW = 4.5 MHz;
UBW and VBW = 1.125 MHz).
Display area
The display area is shown in Fig.4. The given numbers are
pixels at a data rate of 13.5 MHz. The signals are related
to the burstkey and the Vsync. Dependent on the I2C-bus
registers the signals can also be related to the Hsync.
The internal 13.5 MHz data rate is upsampled to the
double frequency (27 MHz) and then fed to the DACs.
The display output can be fine positioned by the I2C-bus in
64 steps of 4 pixels in horizontal direction and 64 steps of
1 line/field in vertical direction.
handbook, full pagewidth
MBE085
228
262.5
18
FT
18
FT
80
FT
104
FT
Vsync
burstkey
H sync
clamp
68
32
864
1/1, 1/3 and 1/4 reduction
1/2 reduction
672
624
Fig.3 Acquisition area.
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