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參數資料
| 型號： | 935257900518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC84 |
| 封裝： | PLASTIC, SOT-189-2, LCC-84 |
| 文件頁數： | 13/42頁 |
| 文件大小： | 289K |
| 代理商： | 935257900518 |
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1996 Jul 08
20
Philips Semiconductors
Preliminary specication
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
Table 21 Logic levels and function of SRCV1
Table 22 Subaddress 6C, 6D
Table 23 Subaddress 6D
Table 24 Subaddress 6E
Table 25 Logic levels and function of PHRES
DATA BYTE
AS OUTPUT
AS INPUT
FUNCTION
SRCV11
SRCV10
0
VS
vertical sync each eld; default after reset
0
1
FS
frame sync (odd/even)
1
0
FSEQ
eld sequence, vertical sync every fourth eld
(PAL = SECAM = 0), eighth eld (PAL = 1) or
twelfth eld (SECAM = 1)
1
not applicable
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 049H (054H)
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG=0to31 (1FH)
DATA BYTE
LOGIC LEVEL
DESCRIPTION
SBLBN
0
vertical blanking is dened by programming of FAL and LAL; default after reset
1
vertical blanking is forced in accordance with
“CCIR 624” (50 Hz) or RS170A (60 Hz)
PHRES
selects the phase reset mode of the colour subcarrier generator; see Table 25
FLC
eld length control; see Table 26
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0
1
reset every two lines or SECAM-specic if bit SECAM = 1
1
0
reset every eight elds
1
reset every four elds
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