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參數資料
| 型號： | 935257900518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC84 |
| 封裝： | PLASTIC, SOT-189-2, LCC-84 |
| 文件頁數： | 26/42頁 |
| 文件大小： | 289K |
| 代理商： | 935257900518 |
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1996 Jul 08
32
Philips Semiconductors
Preliminary specication
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
Fig.15 Digital TV timing.
The data demultiplexing phase is coupled to the internal horizontal phase.
The Cref signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to 0F2h (110h for 50 Hz) in this example in output mode (RCV2S).
handbook, full pagewidth
LLC
CREF
VP(n)
Y(0)
Cb(0)
Y(1)
Cr(0)
Y(2)
Cb(2)
Y(3)
Cr(2)
Y(4)
Cb(4)
DP(n)
RCV2
MBE739
Fig.16 RTCI timing.
(1) Sequence bit:
PAL = logic 0 then (R
Y) line normal; PAL = logic 1 then (R Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
handbook, full pagewidth
128
13
14
19
67 68
01
0
21
RTCI
HPLL
increment
FSCPLL increment (4)
H/L transition
count start
4 bits
reserved
valid
sample
invalid
sample
not used in SAA7182/83
sequence
bit (1)
reset
bit (1)
5 bits
reserved
8/LLC
reserved (2)
MGB700
LOW
time slot:
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