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參數資料
| 型號： | 935260566118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數： | 15/59頁 |
| 文件大?。?/td> | 232K |
| 代理商： | 935260566118 |
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2000 Mar 08
22
Philips Semiconductors
Product specication
Digital video encoder
SAA7128H; SAA7129H
Table 22 Subaddress 51H
Table 23 Subaddress 52H
Table 24 Subaddress 53H
Table 25 Subaddress 54H
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTU[7:0]
LUT for the colour values inserted in case of key colour 2 U detection in the MPEG input
data stream.
LUTU[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTV[7:0]
LUT for the colour values inserted in case of key colour 2 V detection in the MPEG input
data stream.
LUTV[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTY[7:0]
LUT for the colour values inserted in case of key colour 2 Y detection in the MPEG input
data stream.
LUTY[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7
VPSEN
0 = video programming system data insertion is disabled; default state after reset
1 = video programming system data insertion in line 16 is enabled
6
This bit is not used and should be set to logic 0.
5
ENCIN
0 = encoder path is fed with MPB input data; fader is bypassed; default state after reset
1 = encoder path is fed with output signal of fader; see Section 7.1
4
RGBIN
0 = RGB path is fed with MPB input data; fader is bypassed; default state after reset
1 = RGB path is fed with output signal of fader; see Section 7.1
3
DELIN
0 = not supported in current version; do not use
1 = recommended value; default state after reset
2
VPSEL
0 = not supported in current version; do not use
1 = recommended value; default state after reset
1
EDGE2
0 = MPB data is sampled on the rising clock edge; default state after reset
1=MPB data is sampled on the falling clock edge
0
EDGE1
0 = MPA data is sampled on the rising clock edge; default state after reset
1=MPA data is sampled on the falling clock edge
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