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參數資料
| 型號： | 935260566118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數： | 24/59頁 |
| 文件大小： | 232K |
| 代理商： | 935260566118 |
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2000 Mar 08
30
Philips Semiconductors
Product specication
Digital video encoder
SAA7128H; SAA7129H
Table 50 Subaddress 6BH
Table 51 Selection of the signal type on pin RCV1
BIT
SYMBOL
DESCRIPTION
7
SRCV11
These 2 bits dene signal type on pin RCV1; see Table 51
6
SRCV10
5
TRCV2
0 = horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of
“ITU-R BT.656” input (at bit SYMP = HIGH); default state after
reset
1 = horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
4
ORCV1
0 = pin RCV1 is switched to input; default state after reset
1 = pin RCV1 is switched to output
3
PRCV1
0 = polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
state after reset
1 = polarity of RCV1 as output is active LOW, falling edge is taken when input
2
CBLF
When CBLF = 0.
If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontal reference pulse that is
dened by RCV2S and RCV2E, also during vertical blanking interval); default state
after reset.
If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default state after reset.
When CBLF = 1.
If ORCV2 = 1, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is dened by RCV2S and RCV2E, excluding vertical blanking
interval, which is dened by FAL and LAL.
If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal.
1
ORCV2
0 = pin RCV2 is switched to input; default state after reset
1 = pin RCV2 is switched to output
0
PRCV2
0 = polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default state after reset
1 = polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
SRCV11
SRCV10
RCV1
FUNCTION
0
VS
Vertical Sync each eld; default state after reset
0
1
FS
Frame Sync (odd/even)
1
0
FSEQ
Field Sequence, vertical sync every fourth eld (PAL = 0), eighth eld
(PAL = 1) or twelfth eld (SECAM = 1)
11
not applicable
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