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參數資料
| 型號： | 935260802112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 偏轉 |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數： | 20/63頁 |
| 文件大小： | 318K |
| 代理商： | 935260802112 |
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1999 Jul 13
27
Philips Semiconductors
Product specication
I2C-bus autosync deection controllers for
PC/TV monitors
TDA4853; TDA4854
c) VPOS centred (register VPOS = X and control
bit VPC = 1)
d) VLIN = 0 (register VLIN = X and control
bit VSC = 1)
e) VLINBAL = 0 (register VLINBAL = X and control
bit VLC = 1)
f) FHMULT = 0
g) HPARAL = 0 (register HPARAL = X and control
bit HPC = 1)
h) HPINBAL = 0 (register HPINBAL = X and control
bit HBC = 1)
i)
Vertical oscillator synchronized
j)
HSIZE = 255.
9. The output signal at EWDRV (pin 11) may consist of
horizontal pincushion + corner correction + DC shift +
trapezium correction. If the control bit VOVSCN is set,
and the VPOS adjustment is set to an extreme value,
the tip of the parabola may be clipped at the upper limit
of the EWDRV output voltage range. The waveform of
corner correction will clip if the vertical sawtooth
adjustment exceeds 110% of the nominal setting.
10. If fH tracking is enabled, the amplitude of the complete
EWDRV output signal (horizontal pincushion + corner
correction + DC shift + trapezium) will be changed
proportional to IHREF. The EWDRV low level of 1.2 V
remains fixed.
11. First pole of transconductance amplifier is 5 MHz
without external capacitor (will become the second
pole, if the OTA operates as an integrator).
12. Open-loop gain is
at f = 0 with no resistive load
and CBOP = 10 nF [from BOP (pin 3) to GND].
V
BOP
V
BIN
--------------
Vertical and EW adjustments
Fig.5 Adjustment of vertical size.
(1)
I1 is the maximum amplitude setting at register VSIZE = 127,
control bit VOVSCN = 0, control bit VPC = 1,
control bit VSC = 1 and control bit VLC = 1.
VSIZE
I
2
I
1
--------
100%
×
=
VSMOD
I
2
I
1
--------
100%
×
=
handbook, halfpage
t
IVOUT1
IVOUT2
l
2
l
1
(1)
MBG590
Fig.6 Adjustment of vertical position.
(1)
I1 is the maximum amplitude setting at register VSIZE = 127
and control bit VPC = 1.
VPOS
I
2
I
1
–
2I
1
×
----------------------
100%
×
=
handbook, halfpage
t
IVOUT1
IVOUT2
l
2
l
1
(1)
MBG592
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