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參數資料
| 型號： | 935260938557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-205, QFP-44 |
| 文件頁數： | 4/26頁 |
| 文件大小： | 197K |
| 代理商： | 935260938557 |
1998 Feb 05
12
Philips Semiconductors
Objective specication
Multimedia video data acquisition circuit
SAA5284
12 TIMING
Fig.3 Intel mode interface read cycle timing.
handbook, full pagewidth
MGK145
D7 to D0
A2 to A0
RD
RDY
CS0 or CS1
t1
t5
t6
t3
t7
t2
t4
t0
valid address
valid data
B(2)
A(1)
3-state
(1) Event A occurs when RD + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when RD + CS0 + CS1 = 1 (boolean).
Table 3
Intel-mode interface read cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
833
ns
t1
address set-up time before event A
0
ns
t2
address hold time after event B
0
ns
t3
data settling time
88
712
ns
t4
data hold time after event B
0
ns
t5
time from event A until RDY goes LOW
83
170
ns
t6
RDY LOW time
83
530
ns
t7
event B to next event A time
83
ns
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