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參數資料
| 型號： | 935260938557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-205, QFP-44 |
| 文件頁數： | 6/26頁 |
| 文件大小： | 197K |
| 代理商： | 935260938557 |
1998 Feb 05
14
Philips Semiconductors
Objective specication
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
MGK147
t7
t2
t5
t3
t6
t4
t1
D7 to D0
RD(1)
DMACK
DMARQ
valid data
CS
(same signal
as DMACK)
Fig.5 Intel mode interface DMA cycle timing.
(1) Read data pipelined, so no RD LOW to data valid set-up time.
Table 5
Intel-mode interface DMA cycle timing (12 MHz clock)
Note
1. This timing will be up to 3 clock cycles for the first read in DMA transfer.
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t1
DMARQ to DMACK
0
ns
t2
RD LOW to DMARQ LOW
0
212
ns
t3
cycle time
252
ns
t4
DMACK to RD active
0ns
t5
data set-up time
0
90(1)
ns
t6
data hold time
83
ns
t7
data hold from DMACK HIGH
0
83
ns
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