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參數資料
| 型號： | 935261617112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO32 |
| 封裝： | 7.50 MM, PLASTIC, SO-32 |
| 文件頁數： | 11/31頁 |
| 文件大小： | 199K |
| 代理商： | 935261617112 |
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2000 Jan 04
19
Philips Semiconductors
Preliminary specication
Multi-channel lter DAC
UDA1328T
16 AC CHARACTERISTICS (DIGITAL)
VDDD =VDDA = 2.7 to 3.6 V; Tamb = 20 to +85 °C; RL =5k. All voltages referenced to ground (pins 3 and 20); unless
otherwise specied. The typical timing is specied at 44.1 kHz sampling frequency.
Note
1. In the 768fs clock mode, the sampling frequency must be limited to 55 kHz.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Tsys
system clock cycle
fsys = 256fs
35
88
780
ns
fsys = 384fs
23
59
520
ns
fsys = 512fs
20
44
390
ns
fsys = 768fs; note 1
20
30
260
ns
tCWL
LOW-level system clock pulse
width
fsys < 19.2 MHz
30
70
%Tsys
fsys ≥ 19.2 MHz
40
60
%Tsys
tCWH
HIGH-level system clock pulse
width
fsys < 19.2 MHz
30
70
%Tsys
fsys ≥ 19.2 MHz
40
60
%Tsys
tr
rise time
20
ns
tf
fall time
20
ns
Serial input data timing (see Fig.9)
Tcy(CLK)(bit)
bit clock period
140
ns
tCLKH(bit)
bit clock HIGH time
60
ns
tCLKL(bit)
bit clock LOW time
60
ns
tr
rise time
20
ns
tf
fall time
20
ns
tsu(i)(D)
data input set-up time
20
ns
th(i)(D)
data input hold time
0
ns
tsu(WS)
word selection set-up time
20
ns
th(WS)
word selection hold time
10
ns
Microcontroller interface timing (see Figs 6, 7 and 8)
Tcy(CLK)(L3)
L3CLOCK time
500
ns
tCLK(L3)H
L3CLOCK HIGH time
250
ns
tCLK(L3)L
L3CLOCK LOW time
250
ns
tsu(L3)A
L3MODE set-up time
addressing mode
190
ns
th(L3)A
L3MODE hold time
addressing mode
190
ns
tsu(L3)D
L3MODE set-up time
data transfer mode
190
ns
th(L3)D
L3MODE hold time
data transfer mode
190
ns
tsu(L3)DA
L3DATA set-up time
data transfer and addressing mode 190
ns
th(L3)DA
L3DATA hold time
data transfer and addressing mode 30
ns
tstp(L3)
L3MODE halt time
190
ns
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