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參數資料
| 型號： | 935262600518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數： | 25/59頁 |
| 文件大小： | 232K |
| 代理商： | 935262600518 |
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2000 Mar 08
31
Philips Semiconductors
Product specication
Digital video encoder
SAA7128H; SAA7129H
Table 52 Subaddress 6CH
Table 53 Subaddress 6DH
Table 54 Subaddress 6EH
Table 55 Selection of phase reset mode
BIT
SYMBOL
DESCRIPTION
7 to 0
HTRIG[7:0]
These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to
the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH, see
Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Increasing
HTRIG[10:0] decreases delays of all internally generated timing signals. Reference
mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG[10:0] = 4FH (79).
BIT
SYMBOL
DESCRIPTION
7
HTRIG10
These are the 3 MSBs of the horizontal trigger phase code; see Table 52.
6
HTRIG9
5
HTRIG8
4
VTRIG4
Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG
decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG[4:0] = 0 to 31 (1FH).
3
VTRIG3
2
VTRIG2
1
VTRIG1
0
VTRIG0
BIT
SYMBOL
DESCRIPTION
7
SBLBN
0 = vertical blanking is dened by programming of FAL and LAL; default state after reset
1 = vertical blanking is forced in accordance with
“ITU-R BT.624” (50 Hz) or RS170A
(60 Hz)
6
BLCKON
0 = encoder in normal operation mode
1 = output signal is forced to blanking level; default state after reset
5
PHRES1
These 2 bits select the phase reset mode of the colour subcarrier generator;
see Table 55.
4
PHRES0
3
LDEL1
These 2 bits select the delay on luminance path with reference to chrominance path;
see Table 56.
2
LDEL0
1
FLC1
These 2 bits select eld length control; see Table 57.
0
FLC0
PHRES1
PHRES0
DESCRIPTION
0
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default value after reset
0
1
reset every two lines or SECAM specic if bit SECAM = 1
1
0
reset every eight elds
1
reset every four elds
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