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參數(shù)資料
| 型號(hào)： | 935272702518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁(yè)數(shù)： | 32/61頁(yè) |
| 文件大小： | 326K |
| 代理商： | 935272702518 |
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2004 May 18
38
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.20
Internal oscillator register
Table 55 INTOSC (1Bh) bit allocation
Table 56 INTOSC (1Bh) bit description
9.21
Power management register
Table 57 PWRMGT (1Eh) bit allocation
Table 58 PWRMGT (1Eh) bit description
0
CKOENRGB
enables the output CKDATA to be set to high-impedance
0 = active signal
1 = high-impedance
BIT
765432
1
0
Symbol
SWITCHOSC
INTOSCOFF
Default
XXXXXX
0
BIT
SYMBOL
DESCRIPTION
7 to 2
not used
1
SWITCHOSC
enables a multiplexer to be switched; signal insertion on the input of the separator and
coast block, between the internal oscillator and pin CKEXT
0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the
coast, activity detection and sync separator is done
1 = test mode
0
INTOSCOFF
disables the internal oscillator for the separator function, the coast gate and activity
detection
0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast,
activity detection and sync separator is done
1 = disabled
BIT
7654
3
2
1
0
Symbol
SHCKDMX SHCKADC
STBY
DVIRGB
Default
X
0
BIT
SYMBOL
DESCRIPTION
7 to 4
not used
3
SHCKDMX
test bits; should be set to logic 0 for proper operation
2
SHCKADC
test bits; should be set to logic 1 for better performances
1
STBY
enables the RGB block to be forced into the standby mode, except activity detection,
I2C-bus registers. In the standby mode, all outputs are in high-impedance state, except
pin HPDO which is still active. If the IC is in the power-down mode, this bit has no effect
0 = IC active
1 = standby mode
0
DVIRGB
this bit must be set to logic 0 for proper operation
BIT
SYMBOL
DESCRIPTION
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