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參數(shù)資料
| 型號： | 935272703518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 11/61頁 |
| 文件大小： | 326K |
| 代理商： | 935272703518 |
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2004 May 18
19
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
8.8
Sync separator
The sync separator is compatible with TV, HDTV and
VESA standards.
If the green video signal has composite sync on it
(sync-on-green), the SOG function allows to separate the
Chsync and the active video part. The Chsync signal
coming from this SOG function is accessible through
pin CSYNCO.
It is possible to extract the Hsync and the Vsync signals by
using the sync separator from this (C)Hsync signal coming
from SOG or coming from the (C)Hsync input.
This function is able to get rid of the additional
synchronization pulses in vertical blanking like
equalization or serration pulses.
8.9
3-level
When the synchronization pulse of the input of the SOG is
3-level, the system will be able to detect that a 3-level sync
is present and will advise the customer if a change is
observed by setting bit HPDO = 1 and pin HPDO = HIGH.
It is possible to disable this function with bit FTRILEVEL.
When this automatic function is disabled, the manual
mode will only influence the separator circuitry.
9I2C-BUS REGISTER DESCRIPTION
9.1
I2C-bus formats
9.1.1
WRITE 1 REGISTER
Each register is programmed independently by giving its subaddress and its data content.
Table 2
I2C-bus sequence for writing 1 register
Table 3
Byte format for writing 1 register
SDA LINE
DESCRIPTION
S
master starts with a start condition
Byte 1
master transmits device address (7 bits) plus write command bit (R/W=0)
A
slave generates an acknowledge
Byte 2
master transmits programming mode and subregister address to write to
A
slave generates an acknowledge
Byte 3
master transmits data 1
A
slave generates an acknowledge
P
master generates a stop condition
BIT
76543210
Byte 1
device address
R/W
A6
A5
A4
A3
A2
A1
A0
100110
X
0
Byte 2
programming mode
register subaddress
MODE
SA4
SA3
SA2
SA1
SA0
XX
0
Byte 3
data 1
D7
D6
D5
D4
D3
D2
D1
D0
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