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參數資料
| 型號： | 935272703518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數： | 22/61頁 |
| 文件大小： | 326K |
| 代理商： | 935272703518 |
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2004 May 18
29
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.7
PLL control
Table 24 PLLCTRL (0Ah) bit allocation
Table 25 PLLCTRL (0Ah) bit description
9.8
Phase register
Table 26 PHASE (0Bh) bit allocation
Table 27 PHASE (0Bh) bit description
BIT
76543210
Symbol
IP1
IP0
Z2
Z1
Z0
DR2
DR1
DR0
Default
01011100
BIT
SYMBOL
DESCRIPTION
7 to 6
IP[1:0]
charge pump current value to increase the bandwidth of the PLL
00 = 800
A
01 = 1200
A
10 = 1600
A
11 = 2000
A
5 to 3
Z[2:0]
internal resistance value for the VCO lter to be selected
000 = not used
001 = 1.56 k
010 = 1.25 k
011 = 1.00 k
100 = 0.80 k
101 = 0.64 k
110 = 0.51 k
111 = 0.41 k
3 to 0
DR[2:0]
PLL temperature phase drift to be compensated. The optimized value of this register is 001.
These bits add a delay on the clock reference input of the PLL as a function of the
temperature of the die.
000 = +1.75 step phase
001 =
0.3 step phase
010 =
4.3 step phase
011 =
6.2 step phase
100 =
2.2 step phase
BIT
76543210
Symbol
PA4
PA3
PA2
PA1
PA0
VCO2
VCO1
VCO0
Default
00000101
BIT
SYMBOL
DESCRIPTION
7 to 4
PA[4:0]
phase shift value for the clock pixel. See Table 28.
3 to 0
VCO[2:0]
VCO gain control. See Table 29.
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