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參數資料
| 型號： | 935272706518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數： | 26/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706518 |
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2004 May 18
32
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.11
Coast register
Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals the VSYNC input.
Table 37 COAST (12h) bit allocation
Table 38 COAST (12h) bit description
9.12
Horizontal sync selection register
Table 39 HSYNCSEL (13h) bit allocation
Table 40 HSYNCSEL (13h) bit description
BIT
76543210
Symbol
PRE
COAST2
PRE
COAST1
PRE
COAST0
POST
COAST4
POST
COAST3
POST
COAST2
POST
COAST1
POST
COAST0
Default
00000000
BIT
SYMBOL
DESCRIPTION
7 to 5
PRE
COAST[2:0]
programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the
vertical sync signal
4 to 0
POST
COAST[4:0]
programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the
vertical sync signal
BIT
76543210
Symbol
TESTCNT
BYSEPA
HSSEL
HSS
Default
X
0
1
0
BIT
SYMBOL
DESCRIPTION
7 to 4
not used
3
TESTCNT
this bit is used to test the pixel counter
0 = normal mode
1 = test mode
2
BYSEPA
enables the sync separator for the PLL reference to be bypassed
0 = Hsync from the separator
1 = bypass of the sync separator
1
HSSEL
enables either the HSYNC or CHSYNC input signal to be selected
0 = HSYNC input
1 = CHSYNC input
0
HSS
enables either the HSYNC or CHSYNC input signal to be inverted
0 = non-inverted
1 = inverted
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