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參數資料
| 型號： | 935272706518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數： | 29/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706518 |
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2004 May 18
35
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.16
Output register
Table 47 OUTPUT (17h) bit allocation
Table 48 OUTPUT (17h) bit description
1
VSOINVRGB
enables the output VSYNCO to be inverted
0 = non-inverted
1 = inverted
0
FIELDOINV
enables the output FIELDO to be inverted
0 = non-inverted
1 = inverted
BIT
7
6
5
4
3210
Symbol
RGBSEL
TEN
AGCSEL1
AGCSEL0
BLKEN
DMXRGB
ODDARGB SHIFTRGB
Default
0
0000
BIT
SYMBOL
DESCRIPTION
7
RGBSEL
denes which RGB input will be used
0 = input 1
1 = input 2
6
TEN
enables the track and hold operating mode to be selected
0 = mode enable; must be set to logic 0 for proper operation
1 = mode disable
5 to 4
AGCSEL[1:0]
dene the output on pin AGCO
00 = RAGC
01 = GAGC
10 = BAGC
11 = not used
3
BLKEN
inhibits the blanking mode during clamp
0 = blanking active; during the blanking period, the RGB outputs of the ADC are fixed at
the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater
or equal to 0, or forced to 0 if these values are negative.
1 = blanking not active
2
DMXRGB
determines whether all pixels go to port A or if pixels go alternately to port A and B. The
maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode.
0 = port A
1 = port A and B
1
ODDARGB
denes the parity of the pixels
0 = even pixel on port A
1 = odd pixel on port A
0
SHIFTRGB
denes output on port A and B
0 = synchronous
1 = interleaved
BIT
SYMBOL
DESCRIPTION
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