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參數(shù)資料
| 型號： | 9FG1200DF-1LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 1/23頁 |
| 文件大小： | 188K |
| 代理商： | 9FG1200DF-1LF |
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2
& FBD
DATASHEET
1
ICS9FG1200D-1
Description
ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the
. The
can provide outputs up to 400MHz.
Key Specifications
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 100ps across all outputs in 1:1
mode
56-pin SSOP/TSSOP package
RoHS compliant packaging
Features/Benefits
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU
Host Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Functional Block Diagram
STOP
LOGIC
CLK_IN
CLK_IN#
DIF(9:0)
CONTROL
LOGIC
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
VTT_PWRGD#/PD
SPREAD
COMPATIBLE
GEARING PLL
10
IREF
OE(9:0)#
10
SMB_A0
SMB_A1
FS_A_410
STOP
LOGIC
DIF(11:10)
2
OE#
SPREAD
COMPATIBLE
1:1 PLL
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PDF描述 |
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| 9FG1200YG-1LF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 9FG1200YF-1LF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 9FG1201HGLF-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 9FG1201HGLF | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 9FG1201HGLFT | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9FG1200DF-1LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Dual 56-Pin SSOP T/R 制造商:Integrated Device Technology Inc 功能描述:56 SSOP (LEAD FREE) - Tape and Reel |
| 9FG1200DG-1LF | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1200DG-1LFT | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1201CGLF | 制造商:INT_CIR_SYS 功能描述: |
| 9FG1201CGLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標(biāo)準(zhǔn)包裝:1,000 |
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