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參數資料
| 型號： | 9FG1201HGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數： | 1/23頁 |
| 文件大小： | 269K |
| 代理商： | 9FG1201HGLF-T |
ICS9FG1201H
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371E — 01/21/09
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &
FBD
DATASHEET
1
Description
The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential
Buffer Specification. This buffer provides 12 output clocks for CPU
Host Bus, PCI-Express, or Fully Buffered DIMM applications. The
outputs are configured with two groups. Both groups (DIF 9:0) and
(DIF 11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B or CK410B+ main clock
generator, such as the ICS932S421, drives the ICS9FG1201. The
ICS9FG1201H can provide outputs up to 400MHz
Key Specifications
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps within a group
DIF output-to-output skew < 100ps across all outputs
56-pin SSOP/TSSOP package
RoHS compliant packaging
Features/Benefits
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Funtional Block Diagram
STOP
LOGIC
CLK_IN
CLK_IN#
DIF(9:0)
CONTROL
LOGIC
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
VTT_PWRGD#/PD
SPREAD
COMPATIBLE
PLL
10
IREF
OE(9:0)#
10
SMB_A0
SMB_A1
FS_A_410
STOP
LOGIC
DIF(11:10)
2
OE#
GEAR
SHIFT
LOGIC
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
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