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參數資料
型號: A40MX04-2PL68X79
元件分類: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 101 MHz, PQCC68
封裝: PLASTIC, LCC-68
文件頁數: 102/124頁
文件大小: 3142K
代理商: A40MX04-2PL68X79
40MX and 42MX FPGA Families
v6.1
1-73
Table 39
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.9
2.1
2.3
2.7
3.8
ns
tPDD
Internal Decode Module Delay
2.2
2.5
2.8
3.3
4.7
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
tRD2
FO=2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
tRD3
FO=3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
tRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tRD5
FO=8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.6
0.7
1.0
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
2.2
2.4
2.7
3.2
4.5
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tWC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tRCKHL
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
tRCO
Data Valid After Clock HIGH/LOW
4.8
5.3
6.0
7.0
9.8
ns
tADSU
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
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相關代理商/技術參數
參數描述
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A40MX04-2PLG44I 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數:- 邏輯元件/單元數:- RAM 位總計:36864 輸入/輸出數:157 門數:250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA(17x17)
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