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參數(shù)資料
型號(hào)： A40MX04-FPL68X79
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 35/124頁
文件大小： 3142K
代理商： A40MX04-FPL68X79
40MX and 42MX FPGA Families
1- 12
v6.1
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure 1-15. The JTAG test logic circuit can be enabled by
clicking the "Reserve JTAG Pins" check box. Table 5
explains the pins' behavior in either mode.
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to Actel BSDL Files
Format Description application note.
Actel BSDL files are grouped into two categories -
generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs or inouts.
Generic files for MX devices are available on Actel's website
Figure 1-15 Device Selection Wizard
Table 5
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
相關(guān)PDF資料
PDF描述
A40MX04-FPL68 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL84X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPL84 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPQ100X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100
A40MX04-FPQ100 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-FPL84 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A40MX04-FPL84I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL84M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPLG44 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A40MX04-FPLG68 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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