欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: A42MX16-VQG100
廠商: Microsemi SoC
文件頁數: 129/142頁
文件大小: 0K
描述: IC FPGA 140I/O 100VQFP
標準包裝: 90
系列: MX
輸入/輸出數: 83
門數: 24000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-TQFP
供應商設備封裝: 100-VQFP(14x14)
其它名稱: 1100-1057
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 83
Pin Descriptions
CLK/A/B, I/O
Global Clock
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX
devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an
I/O.
DCLK, I/O
Diagnostic Clock
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
Input LOW supply voltage.
I/O
Input/Output
Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.
In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all
dual-purpose pins when configured as I/Os as well.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. The device is placed in the low power mode by
connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.
The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200 s after the LP pin is driven to a logic LOW.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to
provide verification capability. The MODE pin should be terminated to GND through a 10k
Ω resistor so
that the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. Each
diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has
been completed. The pin's probe capabilities can be permanently disabled to protect programmed design
confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
QCLKA/B/C/D, I/O
Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can
function as user I/Os.
Table 1-40 Configuration of Unused I/Os
Device
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
相關PDF資料
PDF描述
A42MX09-TQG176 IC FPGA 104I/O 176TQFP
A42MX16-PQG100 IC FPGA 140I/O 100PQFP
AGL600V5-FGG484 IC FPGA IGLOO 1.5V 484FPBGA
EPF10K30EQC208-2 IC FLEX 10KE FPGA 30K 208-PQFP
RSC44DRYN-S13 CONN EDGECARD 88POS .100 EXTEND
相關代理商/技術參數
參數描述
A42MX16-VQG100A 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA(27X27)
A42MX16-VQG100I 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA(27X27)
A42MX16-VQG100M 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP
A42MX16-VQG100MX3 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 103MHZ/172MHZ 0.45UM 3.3V/5V 100VQF - Trays
A42MX24-1PL84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA(27X27)
主站蜘蛛池模板: 高陵县| 湘潭县| 双牌县| 鄂托克前旗| 杂多县| 揭阳市| 宜良县| 余干县| 任丘市| 民丰县| 全椒县| 彰化市| 黎川县| 手游| 登封市| 辽源市| 万源市| 达拉特旗| 大渡口区| 闻喜县| 建德市| 新郑市| 古蔺县| 随州市| 大新县| 渝中区| 嘉禾县| 甘谷县| 贺州市| 措勤县| 潮安县| 禹城市| 勃利县| 凉城县| 甘肃省| 辉县市| 琼结县| 缙云县| 合水县| 东辽县| 原阳县|