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參數資料
| 型號： | A8450KLBTR-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數： | 14/17頁 |
| 文件大小： | 546K |
| 描述： | IC REG QD BUCK/LINEAR 24-SOIC |
| 標準包裝： | 3,000 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（4） |
| 功能： | 車載 |
| 輸出數： | 4 |
| 電壓/電流 - 輸出 1： | 5.7V，1.2A |
| 電壓/電流 - 輸出 2： | 5V，200mA |
| 電壓/電流 - 輸出 3： | 5V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 6 V ~ 45 V |
| 工作溫度： | -40°C ~ 135°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
Automotive Multioutput Voltage Regulator
A8450
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Test results for this 24-lead SOIC are approximately 35 癈/W
when mounted on a high-thermally conductive PCB (based on
the JEDEC standard PCB, having four layers with buried copper
areas).
The total power that can be applied to the device, P
D(lim)
(W),
is
affected by the maximum allowable device junction temperature,
T
J(max)
(癈), R
窲A
, and the ambient air temperature, T
A
(癈), as
shown in the following formula
P
D(lim)
= (T
J(max)
T
A
) D R
窲A
P
D(lim)
can be estimated based on several parameters, using the
following formula
P
D(lim)
= P
D(Ibias)
+ P
D(V5A)
+ P
D(V5D)
+ P
D(buckdc)
+ P
D(buckac)
+ P
D(BD)
where
P
D(Ibias)
= V
BB
?SPAN class="pst A8450KLBTR-T_2464169_2">
I
BB
P
D(V5A)
= (V
REG
5 V)
?SPAN class="pst A8450KLBTR-T_2464169_2">
I
LOAD(V5A)
P
D(V5D)
= (V
REG
5 V)
?SPAN class="pst A8450KLBTR-T_2464169_2">
I
LOAD(V5D)
P
D(buckdc)
= I
LOAD
2
?SPAN class="pst A8450KLBTR-T_2464169_2">
R
DSON(TJmax)
?SPAN class="pst A8450KLBTR-T_2464169_2">
DC
P
D(buckac)
= I
LOAD
?SPAN class="pst A8450KLBTR-T_2464169_2">
[V
BB
(
5 ns D 14 V)
?SPAN class="pst A8450KLBTR-T_2464169_2">
V
BB
]
?/DIV>
0.5
f
PWM
P
D(BD)
= I
V33BD(max)
?SPAN class="pst A8450KLBTR-T_2464169_2">
(V
REG
4 V) + I
VADJBD(max)
?SPAN class="pst A8450KLBTR-T_2464169_2">
(V
REG
V
ADJ
0.7 V)
and
I
LOAD
= I
LOAD(V33)
+ I
LOAD(VADJ)
+ I
LOAD(V5D)
+ I
LOAD(V5A)
R
DSON
is a function of T
J
. For the purposes of estimating P
D(lim)
,
the relationship can be assumed to be linear throughout the
practical T
J
operating range (see test conditions for R
DSON
in the
Electrical Characteristics table).
DC (duty cycle) is a function of V
BB
and V
REG
. This can be
calculated precisely as
DC = V
REG(off)
D (V
REG(on)
+ V
REG(off)
)
A rough estimate for DC is
DC = (V
REG
+ V
LX
)
D V
BB
I
V33BD(max)
is the maximum current drawn on the V33BD pin. It
is dependent on I
OUTV33
and the h
FE
of the pass transistor.
I
ADJBD(max)
is the maximum current drawn on the VADJBD pin.
It is dependent on I
OUTVADJ
and the h
FE
of the pass transistor.
Overcurrent Protection
The current supplied by the 3.3 V and the 1.2 to 3.3 V adjust-
able regulators is limited to I
CL
. Current above I
CL
is folded back
linearly, as shown in figure 4b. In the case of a shorted load,
the collector current is reduced to 40% of I
CL
?0% , to ensure
protection of the pass transistors. After the short is removed, the
voltage recovers to its regulated level.
The maximum power dissipated in the transistor during a shorted
load condition is:
P
D
H (V
REG
V
OUT
)
?SPAN class="pst A8450KLBTR-T_2464169_2">
(0.4
?SPAN class="pst A8450KLBTR-T_2464169_2">
I
CL
)
where V
OUT
= 0 V.
Low Input Voltage Operation
When the charge pump has ramped enough to enhance the buck
switch, the buck converter switching regulator is enabled. This
occurs at V
BB
H 5.7 V. At that point, the duty cycle, DC, of the
A8450 can be forced to 100% until V
IN
is high enough to allow
the switch to begin operating normally. The point at which nor-
mal switching begins is dependent on ambient temperature, T
A
.
Increases in T
A
cause R
DSON
to increase. Other significant factors
are I
LOAD
, V
REG
, the ESR of the output inductor (L1), and the
forward biasing voltage for the output Schottky diode (D1).
Regulator Bypass
Some applications may not require the use of all four regulators
provided in the A8450. For the regulators that are not used, the
corresponding external components are not needed.
If either or both of the two 5 V regulators are not required by the
application, bypass an unused regulator by not connecting its
output terminal, V5D or V5A. Also, the corresponding output
capacitor, C1 or C2, is not used.
For the 3.3 V regulator and the 1.2 V to 3.3 V adjustable regula-
tor, if either or both are not needed, the corresponding external
components are not used. In addition, if the 3.3 V regulator is not
used, CL33 and V33 are not connected. If the adjustable regula-
tor is not used, CLADJ and FB are not connected. However, to
ensure stability of the A8450, the base drive pin, V33BD or VAD-
JBD, of any unused regulator must be shorted to VREG.
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